PAL — Programmable Array Logic

Synthesis of combinatorial circuits on single Programmable logic device

In this paper two methods of logic synthesis of digital circuits on the base of Programmable Array Logic (PAL) are proposed. First method is the algorithm of synthesis which uses joining PAL outputs by wired-OR connection. Second method uses macrocell feedbacks to construction of complex Boolean functions. Both methods take in account specific internal resources and features of logic structures such as a different number of terms connected to different macrocells, possibility of choice of output signal phase and macrocells with two feedbacks. There are determined conditions of realization of logic functions using these algorithms. Work results are compared to results obtained from other known methods and from MAX+Plus II system.